Power Efficient Hardware Transactional Memory
نویسندگان
چکیده
منابع مشابه
Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions may attempt to commit simultaneously and co-ordination is required before allowing commits to proceed in parallel. In this paper, we propose novel ...
متن کاملHardware-Supported Transactional Memory
In this report, we describe a number of Hardware Transactional Memory (HTM) designs and their basic mechanisms used for better programmability and higher performance than conventional synchronization techniques based on locking. We compare the systems considering their programming model, hardware design challenges, transactional dataset constraints and forward progress guarantees. As high-speed...
متن کاملFaulTM: Fault-Tolerance Using Hardware Transactional Memory
Fault-tolerance has become an essential concern for processor designers due to increasing soft-error rates. In this study, we are motivated by the fact that Transactional Memory (TM) hardware provides an ideal base upon which to build a fault-tolerant system. We show how it is possible to provide low-cost faulttolerance for serial programs by using a minimallymodified Hardware Transactional Mem...
متن کاملHardware Acceleration of Software Transactional Memory
Transactional memory (TM) systems seek to increase scalability, reduce programming complexity, and overcome the various semantic problems associated with locks. Software TM proposals run on stock processors and provide substantial flexibility in policy, but incur significant overhead for data versioning and validation in the face of conflicting transactions. Hardware TM proposals have the advan...
متن کاملOS Support for Virtualizing Hardware Transactional Memory
Transactional memory promises to simplify multithreaded programming. Hardware TM (HTM) implementations promise better performance by augmenting processors with transactional state. However, HTMs interact poorly with the operating system or virtual machine monitor. For example, they often do not tolerate OS actions that virtualize processors and memory, such as context switching and paging. With...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ACM Transactions on Architecture and Code Optimization
سال: 2016
ISSN: 1544-3566,1544-3973
DOI: 10.1145/2875425